1. Field of the Invention
The present invention relates to the design of electronic circuits, and in particular, relates to the design of CMOS integrated circuits.
2. Discussion of Related Art
An MOS transistor operating under the stress of a high gate voltage experiences a drift of the threshold voltage (V.sub.T) over time. Such threshold voltage drift has been extensively studied. For example, the article "Channel Length and Width Effects on NMOS Transistor Degradation under Constant Positive Gate-Voltage Stressing", by K. Wu et al, published in Proceedings of the IEDM (1991), IEEE, pp. 735-38, discusses the geometric effect of such transistor degradation.
In a CMOS comparator, very often a large differential voltage is applied across the comparator's terminal, so that one of two input transistors is in the "on" state, while the other input transistor is in the "off" state. Such a large differential signal may result in a differential stress at the gate terminals of the input transistors, leading to different drifts in the threshold voltages of the input transistors over a long period of time. A measure of the sensitivity of a CMOS comparator is the offset voltage (V.sub.OS), which is the smallest differential voltage received by the comparator necessary to drive the output of the comparator to one of its two output states. Over a long period of time, the different drifts in threshold voltages of the input transistors dominate the drift in V.sub.OS voltage, resulting in serious reliability problems in such a CMOS comparator.